1. Field of the Invention
The present invention relates to programmable logic devices having redundant circuitry.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical conductors that may or may not extend the length of the PLD.
PLDs have configuration elements that may be programmed or reprogrammed. Configuration elements may be realized as RAM bits, flip-flops, EEPROM cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as RAM cells (sometimes referred to a “CRAM” or “configuration RAM”). However, many types of configurable elements may be used including static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term “configuration element” will be used to refer to any programmable element that may be configured to determine functions implemented by other PLD elements.
In some PLDs, the configuration elements are located in a dedicated memory region or regions. In other PLDs, the configuration elements are dispersed throughout the device. In either case, the configuration elements are often treated together as an addressable array, or grid, that may be programmed with configuration data.
PLDs having redundant circuitry can help improve production yields by providing regions on the device that can be repaired by engaging the redundant circuitry. A row based redundancy scheme provides at least one redundant or “spare” row in an array of logic circuitry (e.g. an array of LABs and associated routing). Row based redundancy schemes are described, for example, in commonly assigned U.S. Pat. No. 6,201,404 (entitled “Programmable Logic Device with Redundant Circuitry”) and U.S. Pat. No. 6,344,755 (entitled “Programmable Logic Device with Redundant Circuitry”) and are further described in commonly assigned pending U.S. patent application Ser. No. 10/159,581 (entitled “Programmable Logic Device with Redundant Circuitry”). A repairable region may be defined above the spare row such that, if one of the rows of the logic array is defective, the spare row is activated and each row from the spare row to the bad row replaces the next higher row, thus repairing the defective region.
As the need for high performance in specialized applications grows, it is increasingly useful to provide one or more dedicated blocks designed to serve particular purposes within an array of more general purpose programmable logic circuitry. Aspects of the placement of such dedicated blocks in a logic array are described, for example, in the following commonly assigned pending applications: U.S. patent application Ser. No. 10/057,442 (entitled “PLD Architecture for Flexible Placement of IP Function Blocks”) and U.S. patent application Ser. No. 10/140,911 (entitled “Use of Dangling Partial Lines for Interfacing in a PLD”).
In many instances, however, it is not practical or feasible to provide dedicated blocks that also have redundant circuitry and are repairable through a redundancy scheme. It is nevertheless still desirable to implement redundancy schemes to provide repairable regions of circuitry in a logic array outside of or between regions of dedicated block circuitry.
Thus there is a need to provide a PLD that has repairable regions that may be repaired by invoking a redundancy scheme for a logic array of the PLD but that also includes dedicated blocks of circuitry that may not be repairable. There is a need for a PLD in which such dedicated block regions may be provided that are not repairable while a redundancy scheme in a surrounding logic array may nevertheless be implemented that allows the dedicated block to be programmed with and interface to the surround logic array in normal and redundant modes of the PLD.
As PLDs become more dense, there is also an increasing need to verify data in PLD configuration elements to determine whether elements have flipped values due to environmental or other effects. There is an increasing need to perform such verification during regular operation of the PLD. At the same time, it is desirable, when possible, to reuse signals that are generated to control data shifting during PLD programming to also control other aspects of redundancy during regular (or “user mode”) operation of the programmed PLD. For example, vertical routing to rows may be affected by whether a redundant mode triggering row shifting is engaged. As another example, routing to and from I/O pins along a side of the chip (for example, corresponding to the ends of logic rows) may be effected by whether or not redundancy is engaged to shift rows. In the case of these and other examples, elements to control redundancy within the core or within the I/O areas of the PLD (e.g. tri-state buffers, multiplexors, or other elements used to route signals within the PLD) may need to receive redundancy control signals to properly implement a row-based or other redundancy scheme. However, when dedicated blocks or other regions are present that do not necessarily follow the same pattern of row shifting in a redundant mode as is followed by surrounding regions of a logic array, redundancy control signals used to control programming or during verification may be dynamic rather than fixed (e.g. depending on which portion of the device is presently being programmed). However, if such signals are to be reused during a user mode to control various non-programming aspects of redundancy, it is desirable to provide fixed rather than dynamic values of those signals. Thus, there is a need to reuse redundancy control signals used for programming while still providing fixed signal values during a user mode for various aspects of redundancy control (e.g. core and I/O routing).